Signal delays in PCB traces regarding crosstalk, parity mode
When a signal propagates through a medium, its propagation speed is determined by the signal carrier and surrounding media properties. The signal transmission speed in the PCB (printed circuit board) is related to the plate DK (dielectric constant), the signal mode, the coupling between the signal line and the signal line, and the winding method. As the PCB trace signal rate becomes higher and higher, the timing margin of source-synchronous signals that require higher timing becomes smaller and smaller. Therefore, it is particularly important to accurately know the impact of PCB traces on signal delay at the PCB design stage . This article analyzes the effects of DK, crosstalk, vias, and serpentine windings on signal delay based on simulation.
For the signal to work properly, it must meet certain timing requirements. As the signal rate increases, the development of digital signals has gone from a common synchronous clock to a source synchronous clock and a serial (serdes) signal. In today's consumer electronics, communication server and other industries, source synchronization and serial signals occupy a large proportion. Serial signals such as common PCIE, SAS, SATA, QPI, SFP +, XUAI, 10GBASE-KR and other signals, and source synchronous signals such as DDR signals.
The serial signal sends the data signal and the clock (CLK) signal through the encoding method at the transmitting end, and the data signal and the clock signal are obtained at the receiving end through the clock data recovery (CDR). Because the clock data travels on the same channel, the delay between the serial signal pair and the pair on the PCB is relatively low. It mainly relies on the phase-locked loop (PLL) and the clock data recovery function of the chip.
The source synchronous clock is mainly the DDR signal. In the DDR design, the DQ (data) signal refers to the DQS (data strobe) signal, the CMD (command) signal and the CTL (control) signal refer to the CLK (clock) signal. Because the rate of DQ is CMD & CTL signal rate is 2 times, so the transmission delay requirement between DQ signal and DQS signal is higher than the requirement between CMD & CTL and CLK. Currently the mainstream on the market is DDR1 / ddr2 / ddr3. ddr4 is expected to become the main design of consumer electronics in 2015. With the continuous increase of DDR signal rate, the transmission delay in DDR4 design, especially between DQ and DQS, poses higher challenges for designers.
When designing a PCB, it is necessary to make some equal lengths of the source synchronization signal for timing requirements. Some design engineers have ignored that the equal length of the signal is actually a delay or equal length, or a 'time equal.'
2. Introduction to Transmission Delay
Time delay, also called time delay (TD), usually refers to the time it takes for an electromagnetic signal or an optical signal to pass through the entire transmission medium. The delay on the transmission line is the time it takes for the signal to pass through the entire transmission line.
Propagation delay, also known as propagation delay (PD), usually refers to the time delay of the transmission of electromagnetic signals or optical signals in a unit length transmission medium. It is inversely proportional (reciprocal) to the "propagation speed". The unit is "Ps / inch" or "S / m".
It can be seen from the definition that delay = propagation delay * transmission length (L)
V is the propagation speed, the unit is inch / ps or m / s
The speed of light in a vacuum (3X108 m / s)
Εr is the dielectric constant
PD is the propagation delay, and the unit is Ps / inch or s / m
TD is the delay caused by a signal passing through a transmission line of length L
L is the length of the transmission line, the unit is inch or m
It can be known from the above formula that the propagation delay mainly depends on the dielectric constant of the dielectric material, and the propagation delay depends on the dielectric constant of the dielectric material, the transmission line length, and the geometry of the transmission line cross section (the geometry determines the electric field distribution, and the electric field distribution determines Effective dielectric constant). Strictly speaking, both the delay and the delay depend on the effective dielectric constant around the conductor. In microstrip lines, the effective dielectric constant is greatly affected by the cross-sectional geometry; while crosstalk, its effective dielectric constant is greatly affected by the parity mode; the effective dielectric constant of different winding methods is affected by its winding method. influences.